M. Al-Rawi, L., A. Zidan, K., Dhafer R. Zaghar, D. (2005). Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA. , 9(2), 16-26.
Laiyth M. Al-Rawi; Khamis A. Zidan; Dr. Dhafer R. Zaghar. "Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA". , 9, 2, 2005, 16-26.
M. Al-Rawi, L., A. Zidan, K., Dhafer R. Zaghar, D. (2005). 'Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA', , 9(2), pp. 16-26.
M. Al-Rawi, L., A. Zidan, K., Dhafer R. Zaghar, D. Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA. , 2005; 9(2): 16-26.

Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA

Journal of Engineering and Sustainable Development
Article 1, Volume 9, Issue 2, 2005, Pages 16-26
Authors
Laiyth M. Al-Rawi; Khamis A. Zidan; Dr. Dhafer R. Zaghar
Abstract
There are two methods to implement LUT up to 7-bit depends on the type of Xilinx chip hardware and the software that can use in design and the code generation. The first method implements LUT as a RAM. This method gives high speed and requires a very high cost.
The second method implements LUT as logic gates. This method requires special software and gives a low speed implies.
This paper proposed a modification to the second method that will save the speed of the first method and low cost of the second method. It depends on the design of the LUT. Therefore it will not require special software.
Statistics
Article View: 7
PDF Download: 1


Journal Management System. Powered by iJournalPro.com