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Efficient Hardware Implementation of the Pipelined DES Encryption Algorithm Using FPGA | ||
| Al-Rafidain Engineering Journal (AREJ) | ||
| Article 16, Volume 22, Issue 5, 2014, Pages 212-223 PDF (0 K) | ||
| DOI: 10.33899/rengj.2014.101018 | ||
| Author | ||
| Noor Najeeb Qaqos | ||
| Abstract | ||
| Abstract This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm.This achieved by using a new proposed implementation of the DES algorithm using superpipelinedconcept.DES are simulated using Xilinx 9.2i software with the use of VHDL as the hardware description languageand implemented using Spartan-3E FPGA kit.The DES Encryption algorithm achieved a high throughput of18.327Gbps and 3235 number of Configurable Logic Blocks (CLBs), obtaining the fastest hardware implementation with better area utilization.Comparison is made between the proposed implementation and other recent implementations. The comparison results indicate that a high throughput with optimized resource utilization scan be achieved using a super pipelined concept on the proposed design in a single FPGA chip. | ||
| Keywords | ||
| DES Encryption Algorithm; FPGA; Superpipelining Concept; Spartan; Kit; VHDL; Xilinx ISE | ||
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