RAM-Based Neural Network Parallel Implementation on a Reconfigurable Platform and Its Application for Handwritten Digits Recognition

A. Dawwd, Shefa; Al-Saegh, Ali

doi:10.33899/rengj.2015.101082

	RAM-Based Neural Network Parallel Implementation on a Reconfigurable Platform and Its Application for Handwritten Digits Recognition
Al-Rafidain Engineering Journal (AREJ)
Article 1, Volume 23, Issue 2, 2015, Pages 167-178 PDF (0 K)
DOI: 10.33899/rengj.2015.101082
Authors
Shefa A. Dawwd; Ali Al-Saegh
Abstract
Artificial neural networks (ANNs) are widely used in different areas of nowadays applications. Many challenges are imposed on the practical implementation of ANNs. Some of them are: the number of samples required to train the network; the number of adders, multipliers, nonlinear transfer functions, storage elements; and the speed of calculations in either training phase or recall phase. In this paper, the RAM-based neural network is investigated. No weights, adders, multipliers, transfer functions are required to implement it neither in hardware nor in software, but at a cost of large RAM utilization. In addition, a small number of samples are required for training. However, in hardware implementation, a large size of memory is required to train it.The network is implemented on the FPGA platform. The Stratix IV GX FPGA development board, which is provided on large on board RAM, is used. A considerable speedup of 237is achievedin either training or recalling phases. A comparable error rate of 7.6 is achieved when MNIST (Mixed National Institute of Standards and Technology) database are used to train the network on handwritten digit recognition.
Keywords
Field programmable gate arrays; handwritten digits recognition; Ram; based neural network

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