- All Journals
- Al-Qadisiyah University
- Basrah University
- Kirkuk University
- Mosul University
- The Iraqi Borad for Medical Specialization
- University of Anbar
- University of Technology
- Al Mustafa University
- Al-Zahraa University for Women
- Alnoor University
- Kunooz University
- Misan University
- Ninevah University
- Tikrit University
- University of Al-Hamdaniya
- University of Kerbala
Design and Implementation of a Configurable Real-Time FPGA-Based Geometric Symmetry-CFAR Processer for Radar Target Detection | ||
| Journal of Engineering and Sustainable Development | ||
| Article 1, Volume 15, Issue 3, 2011, Pages 28-41 | ||
| Authors | ||
| Mohammed Hussein Ali; Waleed Khalid | ||
| Abstract | ||
| A Constant False Alarm Rate (CFAR) processor is the signal processing algorithm that controls the rate at which target detection are falsely declared. In this paper, a configurable Field Programmable Gate Array (FPGA)-based hardware architecture for Geometric-symmetry (GS) - CFAR processer for radar target detection is presented. The proposed architecture of this algorithm has been designed using Matlab-Simulink 7.8(R2009a) to deal with parallel structure, so as to obtain system parameters and to test the flow of signal through the system. The design has been converted to behavioral VHDL coding style, as well as a VHDL test bench, Simulink HDL Coder tool has been used to realize hardware directly from Simulink design. The simulation waveforms are obtained using ModelSim Altera 6.1g. Synthesis reports and board programming files have been obtained using the QUARTUS II package. ALTERA-Cyclone III FPGA family with EP3C120F780C7 board has been used as target device for implementation purpose. The post place and route result show that the proposed design can achieve a maximum operating frequency of 115.77MHz which is close to the clock frequency of the prototyping board. | ||
|
Statistics Article View: 116 PDF Download: 74 |
||