S. Omran, S., J. Ibada, A. (2016). FPGA Implementation of MIPS RISC Processor for Educational Purposes. , 24(7), 1745-1761.
Safaa S. Omran; Ali J. Ibada. "FPGA Implementation of MIPS RISC Processor for Educational Purposes". , 24, 7, 2016, 1745-1761.
S. Omran, S., J. Ibada, A. (2016). 'FPGA Implementation of MIPS RISC Processor for Educational Purposes', , 24(7), pp. 1745-1761.
S. Omran, S., J. Ibada, A. FPGA Implementation of MIPS RISC Processor for Educational Purposes. , 2016; 24(7): 1745-1761.

FPGA Implementation of MIPS RISC Processor for Educational Purposes

Journal of University of Babylon
Article 1, Volume 24, Issue 7, 2016, Pages 1745-1761
Authors
Safaa S. Omran; Ali J. Ibada
Abstract
The aim of this research is to design a 32-bit MIPS (Microprocessor without Interlocked Pipeline Stages) for RISC (Reduced Instruction Set Computer) processor. This MIPS can be used for teaching computer structure. This design defines MIPS ISA (Instruction Set Architecture), and divides the processor into two parts: the datapath unit, and the control unit. Next, a top level is implemented by connecting data and instruction memories to the processor. The VHDL (Very High Speed integrated circuit Hardware Description Language) to design hardware modling is used. The single cycle and top level is designed by using (Xilinx ISE Design Suite 13.4) software. This design is conducted on FPGA (Field Programmable Gate Array) Spartan-3AN starter kit and results from the kit are obtained
Keywords
Single cycle; MIPS; RISC; ISA; datapath; VHDL; FPGA
Statistics
Article View: 192
PDF Download: 84


Journal Management System. Powered by iJournalPro.com