- All Journals
- Al-Qadisiyah University
- Basrah University
- Kirkuk University
- Mosul University
- The Iraqi Borad for Medical Specialization
- University of Anbar
- University of Technology
- Al Mustafa University
- Al-Zahraa University for Women
- Alnoor University
- Kunooz University
- Misan University
- Ninevah University
- Tikrit University
- University of Al-Hamdaniya
- University of Kerbala
DESIGN OF A LOW PASS FIR DIGITAL FILTER USING FIELD PROGRAMMABLE GATE ARRAYS (FPGAS) | ||
| AL-TAQANI | ||
| Article 1, Volume 26, Issue 5, 2013, Pages 0-0 | ||
| Authors | ||
| Ahmad Kussay Kayyali; Louay Chachati; Mazin Rejab Khalil | ||
| Abstract | ||
| This paper introduces a design of a low pass finite impulse response digital filter using field programmable gate arrays (FPGAs). A fully parallel distributed arithmetic FIR filter was used to attain speed/ area optimization. . A dual port (4096 x 32) RAM is designed to store the filter output samples. The different modules (elements) composing the system are assembled hierarchically to obtain a hierarchical structure design. Fixed point numbers format is used to avoid data width inflation due to successive multiplication and addition operations. Xilinx integrated software environment (ISE10.1 software) was utilized to develop the VHDL modules. The design could be applied on Xilinx Spartan3E or Vertix family. The system is tested using ISE simulator. The results obtained are compared with the results achieved by simulating the filter on DSP block set of Mat lab 7.2 version software. | ||
|
Statistics Article View: 111 PDF Download: 72 |
||