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Design and Implementation of Efficient and High-Speed Multiplication Circuits Based on Vedic Algorithms | ||
| Journal of Al-Qadisiyah for Computer Science and Mathematics | ||
| Article 1, Volume 10, Issue 1, 2018, Pages 88-99 PDF (0 K) | ||
| Author | ||
| Muthana Yaseen Nawaf Isawi | ||
| Abstract | ||
| The increasing speed of computer processors with each passing day has required the design of arithmetic circuits to be verified as high performance. For this reason; by being observed the computer arithmetic, it enabled faster algorithms to come out and verifications of hardware in terms of the facilities that technology provides. The main aim of the computer arithmetic is the design of the circuits and algorithms that will increase the speed of the numerical process. To this end, the design of arithmetic multiplication circuits with a faster and higher bit length is presented through the efficient bit reduction method in this paper. The developed fast and efficient algorithms for arithmetic multiplication process by using the efficient bit reduction method have been observed in this work. By making changes in some multiplication methods that are based on Vedic math’s, the higher bit length circuits of multiplication circuits in the literature which are 4 bits have been developed by using some basic properties of multiplication like decomposition and bit shifting. Analysis of arithmetic circuits is implemented by verifying functionally with VHDL simulations, getting output signal waveform and measurements of delay time. All the circuits of hardware that are observed have been described via VHDL and the performances of multiplication circuits that are synthesized have been presented via FPGA | ||
| Keywords | ||
| Vedic algorithms; bit reduction; digital multiplier; VHDL; FPGA | ||
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