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Fast Combined Decimal/Binary Multiplier Based on Redundant BCD 4221-8421Digit Recoding | ||
| Basrah Journal for Engineering Science | ||
| Article 6, Volume 17, Issue 1, 2017, Pages 40-47 PDF (0 K) | ||
| Authors | ||
| Mohammed Nabil; Fatemah K Al-Assfor; Mohammed A. Al-Ebadi | ||
| Abstract | ||
| Many applications consider floating point arithmetic as a key component of the computations. Combined decimal/binary arithmetic becomes an important topic supports high-speed decimal/binary applications. A new 64-bit (16×16 digit) the combined decimal/binary multiplier is proposed and implemented in this work that can be used for both fused multiply-add (FMA) and multiplier unit. A new partial products reduction tree is shared between decimal and binary multiplier unit. The valuation and comparison result between the proposed multiplier and the previous most recent works shows 4.66 % less delay than combined decimal/binary multiplier and 19.33 % less delay than the fastest standalone decimal multiplier | ||
| Keywords | ||
| Multiplier; BCD; decimal; binary | ||
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