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Design of n-Bit Adder without Applying Binary to Quaternary Conversion | ||
| Engineering and Technology Journal | ||
| Article 5, Volume 37, 3A, 2019, Pages 106-111 PDF (902.25 K) | ||
| Document Type: Research Paper | ||
| DOI: 10.30684/etj.37.3A.5 | ||
| Authors | ||
| Walaa MH. Khalaf1; Dhafer Zaghar2; Kadhum Al-majdi2 | ||
| 1Computer Engineering Department. College of Engineering, Mustansiriyah University, Baghdad - Iraq | ||
| 2Computer Engineering Department. College of Engineering Mustansiriyah University, Baghdad - Iraq | ||
| Abstract | ||
| Microprocessor has been considered as most important part in ICs manufacturing and making progress since more than 50 years, so increasing microprocessor speed is paid attention in all technologies. ALU is known as the slowest part in microprocessor because of the ripple carry, nowadays microprocessor uses 8-uints as pipeline, each one has 8-bits for implementing 64-bit, working in this form has been captured the microprocessor development and limited its speed for all its computations. Parallel processing and high speed ICs always trying to increase this speed but unfortunately it remains limited. The contemporary solution for increasing microprocessors speed is the Multiple Valued Logic (MVL) technology that will reduce the 8-bits to 4-qbits, this paper proposes a new design of a 2-qbit full adder (FA) as a basic unit to implement MVL ALU (AMLU) that has 8-units as pipeline, each one consists of 4-qbits to implement 32-qbit which is equivalent to 64-bit, without applying binary to quaternary conversion and vice versa. The proposed design increases microprocessors speed up to 1.65 times, but also a little increase of implementation. | ||
| Keywords | ||
| CCCi; Full Adder (FA); Multi Valued Logic (MVL); Quaternary Logic | ||
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