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State Space Parallelization Method for a 16-Bit Turbo Encoder | ||
| Engineering and Technology Journal | ||
| Article 9, Volume 37, 12A, 2019, Pages 553-557 PDF (726.9 K) | ||
| Document Type: Research Paper | ||
| DOI: 10.30684/etj.37.12A.9 | ||
| Authors | ||
| Maha A. Fleah; Qusay F. Al-Doori | ||
| Control and Systems Eng., University of Technology - Iraq | ||
| Abstract | ||
| Turbo codes are widely used in digital communication systems. Their ability to reach the Shannon channel capacity made it the choice for most of the communication systems. Due to the huge amount of the transmitted data, there is a need to increase the processing speed of the encoders. The researchers used the state space technique to enhance the throughput of the turbo encoder. They apply it to increase the turbo encoder throughput from one bit per cycle up to 8 bit per cycle. The researchers applied the state space method to a three-flip flop, eight state Recursive Systematic Convolution Code circuit to achieve their goal. In this paper, we explored the state space technique and applied it to a four flip-flop Recursive Systematic Convolution Code circuit so that we can achieve a throughput of 16 bit per cycle. The circuit was designed and tested using MATLAB then implemented using FPGA to verify its operation. | ||
| Keywords | ||
| Turbo encoder; parallel concatenated; Recursive Systematic Code (RSC) | ||
| References | ||
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