Thannoon, H., Hashim, I. (2024). FPGA Implementation of Efficient Adaptive Filter Incorporating Systolic Architecture. , 42(2), 261-275. doi: 10.30684/etj.2023.142877.1548
Harith H. Thannoon; Ivan A. Hashim. "FPGA Implementation of Efficient Adaptive Filter Incorporating Systolic Architecture". , 42, 2, 2024, 261-275. doi: 10.30684/etj.2023.142877.1548
Thannoon, H., Hashim, I. (2024). 'FPGA Implementation of Efficient Adaptive Filter Incorporating Systolic Architecture', , 42(2), pp. 261-275. doi: 10.30684/etj.2023.142877.1548
Thannoon, H., Hashim, I. FPGA Implementation of Efficient Adaptive Filter Incorporating Systolic Architecture. , 2024; 42(2): 261-275. doi: 10.30684/etj.2023.142877.1548

FPGA Implementation of Efficient Adaptive Filter Incorporating Systolic Architecture

Engineering and Technology Journal
Volume 42, Issue 2, February 2024, Pages 261-275    PDF (1.19 M)
Document Type: Research Paper
DOI: 10.30684/etj.2023.142877.1548
Authors
Harith H. Thannoon* ; Ivan A. Hashim
Electrical Engineering Dept., University of Technology-Iraq, Alsina’a street, 10066 Baghdad, Iraq.
Abstract
This paper introduces an approach that capitalizes on the retimed delay concept to enhance adaptive filters' operational efficiency. In particular, it introduces an adaptive filter configuration with minimal critical path delay. The adaptive filters, namely Least Mean Square (LMS), Recursive Least Square (RLS), and Affine Projection (AP) have been meticulously designed through the utilization of the Xilinx System Generator (XSG). The approach is based on a systolic architecture, which aims to reduce the critical path delay by minimizing the number of processing elements, including adders and multipliers, in each iterative process. Notably, the critical path of the proposed filters has been successfully reduced to a single multiplier. Moreover, the non-restoring division algorithm has been employed to execute division operations within the FPGA for the purposes of weight updates in the equations of RLS and AP filters. The performance of the proposed filters was evaluated using many filter design metrics, including SNR, power consumption, steady-state MSE, convergence speed, and complexity. The improvement in SNR was 4.3%, 8.2%, and 10% for RDLMS, RDRLS, and RDAP filters, respectively. The power consumption was reduced by about 40.5%, 28.6%, and 5.9% for RDLMS, RDRLS, and RDAP filters. Moreover, the results show significant improvement in the convergence speed. The proposed filters can efficiently remove PLI noise from ECG signals with high speed and low power consumption at the cost increase in complexity, but they are still implementable on the FPGA platform. The proposed filters were implemented using the Spartan-6 xc6slx16-2csg324 FPGA.

Highlights
  • This paper presents the refinement of systolic-based adaptive filters to mitigate critical path delay.
  • The impact of utilizing a systolic architecture on filtering performance was evaluated.
  • LMS, RLS, and AP algorithms were implemented within an FPGA platform.
Keywords
Adaptive filter Systolic FPGA non; restoring LMS
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