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Efficient Implementation of Serial Search Synchronization Sub - system for Direct Sequence Spread Spectrum System Using FPGA | ||
| Engineering and Technology Journal | ||
| Volume 24, Issue 2, February 2005, Pages 140-145 PDF (1.05 M) | ||
| Document Type: Research Paper | ||
| DOI: 10.30684/etj.24.2A.8 | ||
| Authors | ||
| Waleed Amen AL - Jauhar1; Hikmat Najem Abdullah2 | ||
| 1Dep. of Electrical Eng., University of Baghdad. | ||
| 2Dep. of Electrical Eng., University of Al-Mustansiryah | ||
| Abstract | ||
| Abstract : A complete synchronization detection sub - system for direct sequence spread spectrum ( DS / SS ) system has been designed and implemented using Xilinx - Virtex Field Programmable Gate Array ( FPGA ) device . Then , a number of modifications has been made to the original sub - system to obtain optimum FPGA cost / delay optimization . For this purpose , the 8 bit representation of BPSK DS / SS signal was replaced by only one bit representation with the same performance at middle values of signal - to - noise ratio . The synthesis and implementation reports of VHDL programs that written to model both systems are developed for comparison purpose . These reports show that the modified implementation offers a cost reduction factor of 95.8 % and delay reduction factor of 50 % as compared with the traditional one . | ||
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