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Multidimensional Systolic Arrays of LMS AlgorithmAdaptive (FIR) Digital Filters | ||
| Al-Khwarizmi Engineering Journal | ||
| Article 1, Volume 5, Issue 1, 2009, Pages 83-93 | ||
| Authors | ||
| Bakir A. R. Al-Hashemy; Riyadh A.H. AL-Helali | ||
| Abstract | ||
| A multidimensional systolic arrays realization of LMS algorithm by a method of mapping regular algorithm onto processor array, are designed. They are based on appropriately selected 1-D systolic array filter that depends on the inner product sum systolic implementation. Various arrays may be derived that exhibit a regular arrangement of the cells (processors) and local interconnection pattern, which are important for VLSI implementation. It reduces latency time and increases the throughput rate in comparison to classical 1-D systolic arrays. The 3-D multilayered array consists of 2-D layers, which are connected with each other only by edges. Such arrays for LMS-based adaptive (FIR) filter may be opposed the fundamental requirements of fast convergence rate in most adaptive filter applications. | ||
| Keywords | ||
| Adaptive signal processing; LMS algorithm; VLSI signal processing | ||
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