- All Journals
- Al-Qadisiyah University
- Basrah University
- Kirkuk University
- Mosul University
- The Iraqi Borad for Medical Specialization
- University of Anbar
- University of Technology
- Al Mustafa University
- Al-Zahraa University for Women
- Alnoor University
- Kunooz University
- Misan University
- Ninevah University
- Tikrit University
- University of Al-Hamdaniya
- University of Kerbala
Reduction of the error in the hardware neural network | ||
| Al-Khwarizmi Engineering Journal | ||
| Article 1, Volume 3, Issue 2, 2007, Pages 1-7 | ||
| Author | ||
| Dhafer r. Zaghar | ||
| Abstract | ||
| Specialized hardware implementations of Artificial Neural Networks (ANNs) can offer faster execution than general-purpose microprocessors by taking advantage of reusable modules, parallel processes and specialized computational components. Modern high-density Field Programmable Gate Arrays (FPGAs) offer the required flexibility and fast design-to-implementation time with the possibility of exploiting highly parallel computations like those required by ANNs in hardware. The bounded width of the data in FPGA ANNs will add an additional error to the result of the output. This paper derives the equations of the additional error value that generate from bounded width of the data and proposed a method to reduce the effect of the error to give an optimal result in the output with a low cost. | ||
| Keywords | ||
| Neural; processor; DSP; FPGA; ISE; i software; adder; multiplier | ||
|
Statistics Article View: 122 PDF Download: 101 |
||