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FPGA Implementation of Multiplierless DCT/IDCT Chip | ||
| Al-Rafidain Engineering Journal (AREJ) | ||
| Article 10, Volume 19, Issue 4, 2011, Pages 55-67 PDF (0 K) | ||
| DOI: 10.33899/rengj.2011.26797 | ||
| Authors | ||
| Dr. Ahlam Fadhil Mahmood; Abdulkreem Mohameed Salih | ||
| Abstract | ||
| Abstract The advance of mobile electronics technology has produced handheld appliances allowing both wireless voice and data communications. One of the most important operations in the realm of digital signal and image processing is the 2-D Discrete Cosine Transform. This paper presents a multiplierless two dimensional Discrete Cosine Transform/Inverse Discrete Cosine Transform (DCT/IDCT) based on the transpose method. In this method the 2-D DCT is obtained by taking two 1-D DCTs in series. The input data is first divided into NxN blocks and the row-wise 1-D DCT of each block is taken, the intermediate transposition is then determined and a column-wise 1-D DCT is ascertained which gives the 2-D DCT of the data. The hardware implementation is parallel, pipelined and decomposed the coefficients matrix into four power of two term(i.e:16 ) to perform shift and add operations instead of multipliers(i.e 16); it costs only 1,443 slice , and runs at maximum frequency of 82.8 MHz with a very high process throughput of 991.2 Megabits/sec when synthesized onto Spartan3-E XC3S500 FPGA device. The proposed 2-D DCT/IDCT design achieving the most demanding real-time requirements of CODEC standardized frame resolutions and rates. | ||
| Keywords | ||
| KEYWORDS; IDCT; FPGA; Mutilplierless; Image Processing | ||
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