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VHDL Implementation of Hybrid Block Cipher Method (SRC) | ||
| Engineering and Technology Journal | ||
| Article 1, Volume 28, Issue 5, 2010, Pages 953-963 PDF (243.85 K) | ||
| DOI: 10.30684/etj.28.5.8 | ||
| Authors | ||
| Ashwaq T. Hishem; Najwa M. Hassen; Ekhlas M. Farhan | ||
| Abstract | ||
| This paper discusses the hardware design of the hybrid block cipher method that combines the RC6 cipher and the Serpent cipher. The block size is 128 bits, and the key can be any length up to 256 bytes. This algorithm is designed to take advantage of the powerful, which is supported by RC6 and Serpent encryption algorithms with overcoming their weaknesses, resulting in a much improved security/performance tradeoff over existing ciphers. The discussion addresses hardware design and VHDL implementation of the key expansion algorithm and the encryption algorithm. | ||
| Keywords | ||
| SRC; Serpent; Cryptography; VLSI design | ||
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