Design of Hierarchical Architecture of Multilevel Discrete Wavelet Transform Using VHDL Language

Fawwaz Shareef, Waleed

doi:10.30684/etj.28.7.7

	Design of Hierarchical Architecture of Multilevel Discrete Wavelet Transform Using VHDL Language
Engineering and Technology Journal
Article 1, Volume 28, Issue 7, 2010, Pages 1350-1360 PDF (336.76 K)
DOI: 10.30684/etj.28.7.7
Author
Waleed Fawwaz Shareef
Abstract
The wide spread of devices that use image processing in its functions, like cellular phone and digital cameras, increases the need for specialized processors for these functions as a replacement for software programs that consume more time and resources. This paper presents a hardware description for discrete wavelet transform (DWT) module in VHDL language. The design involves the forward DWT (fDWT) and its inverse (iDWT) characterized by variable number of transformation levels, ranging from one level to seven levels. Each one of these two modules is designed as hierarchical scheme that uses one-dimensional processing module twice to represent two-dimensional processing. The module can be used repeatedly on the same image for multilevel processing. Three versions of the design are presented (v64, v128 and v256), each one adapted different image size. Synthesis process showed that the design frequency is about 56MHz. The simulation process showed that the maximum possible rounding error is about 0.012%. This resolution with the variable number of processing level adapts this design to fit in many applications. Finally, a comparison of the proposed design with other related work is presented, considering performance and specifications.
Keywords
Wavelet; image coding; VHDL

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