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FPGA Simulation of Type-3 Feistel Network of The 128 bits Block Size Improved Blowfish Cryptographic Encryption | ||
| Engineering and Technology Journal | ||
| Article 1, Volume 28, Issue 9, 2010, Pages 1707-1718 PDF (306.41 K) | ||
| DOI: 10.30684/etj.28.9.1 | ||
| Authors | ||
| Ashwaq Talib Hashim; Yousra A. Mohammed; Ekhlas H. Karam | ||
| Abstract | ||
| Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions , therefore this paper investigates a hardware design to efficiently implement block ciphers in VHDL based on FPGA’s. This hardware design is applied to the new secret-key block cipher called 128-bits improved Blowfish is proposed which is an evolutionary improvement of 64-bits Blowfish designed to meet the requirements of the Advanced Encryption Standard (AES) to increase security and to improve performance. The proposed algorithm will be used a variable key size up to 192 bytes. It is a Type-3 Feistel network iterated simple function 16 times. The resources used to implement the design just described are: the VHDL hardware description language, an FPGA platform from Xilinx and the Xilinx Synthesis Technology (XST) software synthesis tools that belong to ISE 9.2i package. The device of choice is the XCV600-4fg680 belonging to the Virtex family of devices. In this paper, a pipeline and sequential methods are used to get a high througput (2.893Gbps) and a low area hardware design respectively. | ||
| Keywords | ||
| Cryptographic; Blowfish; VHDL; and FPGA | ||
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