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DESIGN OF A HARDWARE TWO-LAYER PERCEPTRON NEURAL NETWORK USING FIELD PROGRAMMABLE GATE ARRAYS (FPGAS) FOR SPEECH RECOGNITION | ||
| AL-TAQANI | ||
| Article 1, Volume 24, Issue 8, 2011, Pages 0-0 | ||
| Authors | ||
| Mazin Rejab Khalil; Maan Mohamad Shikr; Ahmad Kussay Kayali | ||
| Abstract | ||
| Multi-layer perceptron neural networks (MLPNN) have been used in many applications in science and engineering. Real time applications necessitate the hardware implementation of MLPNN. This paper introduces a method to design a two-layer perceptron neural network using field programmable gate arrays (FPGAs). The different modules composing the system are designed using very high speed description language (VHDL) and assembled hierarchically. Fixed point numbers format is used to avoid data width inflation due to successive multiplications and additions. Piece wise second-order approximation of the sigmoid function is adopted. Xilinx ISE 9.2i software was used to develop and simulate the VHDL modules. The designed neural network is configured on Xilinx Spartan 3e starter kit, its functionality is tested by applying it as a discriminating unit in a certain speech recognition system. | ||
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