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BICMOS RF CIRCUIT DESIGN LNA | ||
| AL-TAQANI | ||
| Article 1, Volume 23, Issue 4, 2010, Pages 12-24 | ||
| Author | ||
| Odai A. Wadea | ||
| Abstract | ||
| This paper is concerned with the optimal design and simulation of Low Noise Amplifier for mobile communications operating at 1.5 GHz, 1.5 V and 0.25 mm channel length. The minimization of noise figure and required chip area for fabrication are the most important parameters to be investigated, therefore the optimization technique applied in this paper is to obtain the optimum structure parameters design values and to provide the minimum noise factor together. A modified new structure is used to minimize the chip area that is required for the fabrication of the amplifier on single chip. Electronic workbench (EWB) is used to simulate the designed structures to obtain the best results in such simulation. | ||
| Keywords | ||
| Very Large Scale Integration; Radio Frequency Integrated Circuit; Complementary Metal Oxide Semiconductor; Surface Mount Device; and Signal to Noise Ratio; Low Noise Amplifier | ||
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