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FPGA Based Implementation of Convolutional Encoder- Viterbi Decoder Using Multiple Booting Technique | ||
| Al-Rafidain Engineering Journal (AREJ) | ||
| Article 13, Volume 18, Issue 6, 2010, Pages 70-80 PDF (0 K) | ||
| DOI: 10.33899/rengj.2010.34888 | ||
| Authors | ||
| Yahya Taher Qassim; Dr. Dhafir A. Alneema | ||
| Abstract | ||
| Abstract Convolutional encoding is considered one of the forward error correction schemes. It is an essential component of wireless communication systems such as the third generation (3G) mobile systems, which utilize some formulation of Convolutional encoding usually decoded via Viterbi decoders. There are different structures of Convolutional encoding which impart different requirements on the decoder. The Viterbi decoder segments with slight modifications can be used on systems with different constraint lengths, frame size and code rates. In this research, the design and implementation of Convolutional encoder with constraint length 3 and rate 1/2, and Viterbi decoder on Spartan 3E FPGA Starter kit (supported with XC3S500E) using multiple booting technique has been presented. VHDL language is used as a design entry. In the starter kit mentioned above, two designs are implemented on the flash memory using the multiple booting technique: the Convolutional encoder and the Viterbi decoder. The FPGA is configured with the specified design depending on the loaded program from the Intel flash memory. With this way of configuration, the FPGA itself can operate as a Convolutional encoder or Viterbi decoder that gain benefit through the reuse of the same hardware. Key words : Convolutional encoder, Viterbi decoder, multiple booting technique and FPGA. | ||
| Keywords | ||
| Key Words; Viterbi decoder; multiple booting technique and FPGA | ||
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