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FPGA versus Subword Parallelism Implementations for a VQ Problem | ||
| AL-MANSOUR JOURNAL | ||
| Article 1, Volume 0, Issue 14, 2017, Pages 244-258 | ||
| Authors | ||
| Laith Baker Salman; Mahmoud Shuker Mahmoud | ||
| Abstract | ||
| Vector Quantization (VQ) is a widely used algorithm in image data compression, voice compression, and more generally in signal processing. VQ is a generalization of scalar quantization and it is a codebook-based method. Unfortunately, designing a codebook that best represents the set of input vectors is an NP-hard problem. One of the successful solutions to this problem is to parallelize it. In recent years, high performance computing system have become more and more widespread, especially with the advent of highly flexible Field Programmable Gate Array (FPGA) and relatively cheap general purpose processors supported with SIMD instructions (MMX, SSE). FPGAs are used in situation where the implemented algorithm is highly parallel. Arrays of processing units can be built in a single FPGA chip to perform the required process. The SIMD media ISA extensions for general-purpose processors has usually been to utilize Sub-word Level Parallelism (SLP) with existing hardware. In this paper, two methods for parallelizing VQ are proposed. The first is a hardware-based parallelism using FPGA; and the second is a software-based parallelism using SIMD instructions. Finally, a comparison between the two proposed methods is obtained. | ||
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