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Design and Implementation of a High Resolution Two Counter Digital Pulse Width Modulation | ||
| Engineering and Technology Journal | ||
| Article 1, Volume 27, Issue 7, 2009, Pages 1260-1269 PDF (363.5 K) | ||
| DOI: 10.30684/etj.27.7.3 | ||
| Author | ||
| Jassim K. Hmood | ||
| Abstract | ||
| This paper presents a high resolution Digital Pulse Width Modulation "DPWM" for the voltage regulator application. The PWM signal is generated by using two fast clock counters. In this approach, the pulse width is combined from two parts depending on two counter schemes. MSBs of the DPWM generates first part of pulse that achieved by a first counter-phase comparator scheme, and the LSBs of the DPWM generates second part of pulse that obtained through a second counter- phase comparator scheme. The resolution of present pulse width depends on the resolution of second counter. The developed pulse width modulator has high precision, good linearity, and wide duty cycle range. Further, it can be flexibly reconfigured for multi-phase PWM operation with no restriction on duty cycle range. In this work, a 714 kHz switching frequency DPWM module with 9- bit resolution is tested by simulation program | ||
| Keywords | ||
| Pulse width modulation; voltage regulator; counters; buck converter | ||
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