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Logic gate verification using Neural Network | ||
| Journal Of AL-Turath University College | ||
| Article 1, Volume 0, Issue 7, 2017, Pages 202-226 | ||
| Authors | ||
| Aseel Mousa Ja; | ||
| Abstract | ||
| This work concentrates on showing the applicability of neural networks to The field of design automation (CAD system), especially in the area of hardware verification. The proposed algorithm is valid for combinational circuits verification, which is based on merging two of the well-known learning algorithms for neuralnetworks. The first one, Perceptron Convergence Procedure, which is usedfor learning the functions of the standard logic gates, in order to simulate thewhole circuit. The second, is the learning algorithm of Back-propagation neuralnetworks, which is modified to be used in the verification of the hardware design. Also, it predicts the gate that causes the malfunction in the incorrect design. An important part of the designed systemis the graphical representation of the hardware, which is an interactive user interface for the hardware description. There is a translator that translate the graphical description into a multi-layer feedforward neural network. After describing the hardware design, and stating it's specifications, which includes two methods of specifications: the truth table method and the logical statements method. The verification step begins. | ||
| Keywords | ||
| logic; gate | ||
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