Design and Simulation of Digital PLL Synchronizer for BPSK and QPSK Based on Software Defined Radio

T.  Ziboon, H.; A. Thabit, A.

doi:10.30684/etj.27.10.9

	Design and Simulation of Digital PLL Synchronizer for BPSK and QPSK Based on Software Defined Radio
Engineering and Technology Journal
Article 1, Volume 27, Issue 10, 2009, Pages 2008-2026 PDF (328.86 K)
DOI: 10.30684/etj.27.10.9
Authors
H. T. Ziboon; A. A. Thabit
Abstract
This paper presents a design and simulation of digital PLL synchronizer, using Costas loop based on SDR for high frequency communication systems. Design parameters are selected for each unit of the proposed systems in order to accommodate SDR requirements. Different techniques for carrier recovery based on SDR are discussed. PLL techniques is chosen for synchronization, since it is one of the most active synchronization techniques. BPSK and QPSK synchronizers for coherent receivers have been designed and simulated based on SDR using both Costas loop and modified Costas loop. The simulation result shows that these two systems are reliable in recovering the carrier phase and frequency when significant frequency and phase are present. Simulation result shows that the BPSK system has Pe =10-3 at Eb / No equal to 8.5 dB in the presence of AWGN and has the ability to track frequency offset up to 1200Hz with 2*10 -4 probability of bit error at Eb / No equal to 20 dB. This system can track phase offset 45 o with Pe =10-4 at Eb / No equal to 20 dB. For QPSK system, the probability of bit error 10-3 at Eb / No =9dBand has the ability to track frequency offset 300 Hz and phase offset=9 o with Pe =10-3 at Eb / No equal to 20dB.
Keywords
SDR; PLL; synchronization; Carrier recovery; Costas loop

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