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Digital Hardware Implementation of Artificial Neurons Models Using FPGA | ||
| Al-Rafidain Engineering Journal (AREJ) | ||
| Article 3, Volume 17, Issue 2, 2009, Pages 12-24 PDF (0 K) | ||
| DOI: 10.33899/rengj.2009.38764 | ||
| Authors | ||
| ad Ahmed Al-Kazzaz; Rafid Ahmed Khalil | ||
| Abstract | ||
| Abstract This paper present the digital implementation of multiply-accumulate (MAC) circuit of artificial neuron using FPGA (Field Programmable Gate Array) including three types of nonlinear activation functions: hardlims, satlins and tansig. A VHDL hardware description Language codes are used to implement the neuron using XC3S500E-FG320 Xilinx FPGA device. The simulation results obtained with Xilinx Foundation 8.2i software are presented. The results are analyzed in terms of usage percentage of chip resources and maximum working frequency. Keyword:- Artificial Nouron , FPGA , Neural Network | ||
| Keywords | ||
| Keyword; Artificial Nouron; FPGA; neural network | ||
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