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Reconfigurable Self-Organizing Neural Network Design and it's FPGA Implementation | ||
| Al-Rafidain Engineering Journal (AREJ) | ||
| Article 14, Volume 17, Issue 3, 2009, Pages 99-115 PDF (0 K) | ||
| DOI: 10.33899/rengj.2009.42925 | ||
| Authors | ||
| Basma M. K. Younis; Basil Sh. Mahmood; Fakhraldeen H. Ali | ||
| Abstract | ||
| Abstract The use of Kohonen self-organizing feature maps in real time applications requires high computational performance, especially for embedded systems and hence neural network chips are essential. A digital architecture of Kohonen neural network with learning capability and on-chip adaptation and storage is proposed with the implementation of Kohonen Self-Organizing Map (SOM) neural networks on the low-cost Spartan-3 FPGAs. The architecture of this digital chip based on the idea that some assumptions for the restrictions of the algorithm can simplify the implementation. Using the Manhattan distance, a special treatment of the adaptation factor, and neighborhood functions will decrease the necessary chip area so that a high number of processing elements can be integrated on one chip. Keywords: FPGA, Weight Vectors, Manhattan distance, Learning | ||
| Keywords | ||
| KEYWORDS; Weight Vectors; Manhattan distance; learning | ||
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