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Floating Point Optimization Using VHDL | ||
| Engineering and Technology Journal | ||
| Article 1, Volume 27, Issue 16, 2009, Pages 3023-3049 PDF (297.86 K) | ||
| DOI: 10.30684/etj.27.16.11 | ||
| Author | ||
| Manal Hammadi Jassim | ||
| Abstract | ||
| Due to inherent limitations of the fixed-point representation, it is sometimes desirable to perform arithmetic operations in the floating-point format. Although an established standard for floating-point arithmetic exists, optimal hardware implementations of algorithms require use of floating-point formats different from the ones specified in the standard. Hardware modules for floating-point format control, arithmetic operators and conversion to and from any fixed-point format are presented. Synthesis results for arithmetic operator modules in several floating-point formats, including the IEEE single precision format, Synthesis and processing results for both implementations are shown and compared | ||
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