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Fpga Design And Implementation Of A Scan Conversion Graphical Sub-System | ||
| Al-Rafidain Engineering Journal (AREJ) | ||
| Article 14, Volume 16, Issue 4, 2008, Pages 80-92 PDF (0 K) | ||
| DOI: 10.33899/rengj.2008.44735 | ||
| Authors | ||
| Amar I. Dawod; Fakhraldeen H. Ali | ||
| Abstract | ||
| Abstract One Major modeling primitive in the field of Computer Graphics is a planar polygon. This polygon can have an arbitrary number of vertices and different shapes. In this paper a graphic sub-system is designed and implemented using Field Programmable Gate Array ( FPGA ). One of the main tasks of the hardware designed is scan-converting convex planar polygons required to update an image in the image memory or video RAM which is used as a Frame Buffer. A facility to read the pixels (Picture Elements), from the frame buffer, for display on the monitor of the computer is also included in the design. Keywords: frame buffer, scan-conversion, polygons, pixels, FPGA | ||
| Keywords | ||
| KEYWORDS; scan; conversion; polygons; pixels; FPGA | ||
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