Yazen A. Khalil, D. (2011). Proposed Design and Implementation of a Schematic FPGA-BASED Binary Arithmetic Multiplier. , 11(1), 106-113.
Dr. Yazen A. Khalil. "Proposed Design and Implementation of a Schematic FPGA-BASED Binary Arithmetic Multiplier". , 11, 1, 2011, 106-113.
Yazen A. Khalil, D. (2011). 'Proposed Design and Implementation of a Schematic FPGA-BASED Binary Arithmetic Multiplier', , 11(1), pp. 106-113.
Yazen A. Khalil, D. Proposed Design and Implementation of a Schematic FPGA-BASED Binary Arithmetic Multiplier. , 2011; 11(1): 106-113.

Proposed Design and Implementation of a Schematic FPGA-BASED Binary Arithmetic Multiplier

IRAQI JOURNAL OF COMPUTERS, COMMUNICATIONS, CONTROL AND SYSTEMS ENGINEERING
Article 1, Volume 11, Issue 1, 2011, Pages 106-113
Author
Dr. Yazen A. Khalil
Abstract
Abstract:
This article presents a proposed design and implementation of an 8-bit Arithmetic Multiplier based on FPGA (Field Programmable Gate Array). The design is implemented a schematic FPGA way using CPLD (Complex Programmable Logic Device) development board SN-PLDE2. The development board contains an FPGA device EPF8282ALC4-4 (5000 gates account) of Altera FLEX8000 family (Flexible Logic Element MatriX) with the other necessary peripherals. The proposed design is achieved under MAXplus2 V10.1 software for FPGA programming. The designed arithmetic multiplier is tested using an experiment board (SN-PLDE3A). The results show both efficient usage and high performance including the accuracy and the fast operation.
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