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Minimizing Power Consumption in Combinational Logic Circuits by Reducing Switching Activity | ||
| Thi-Qar University Journal for Engineering Sciences | ||
| Article 1, Volume 2, Issue 1, 2011, Pages 118-125 | ||
| Author | ||
| Nahla D. Habeeb | ||
| Abstract | ||
| The aim of the present paper is to investigate the minimization of the power consumption in combinational circuits by reducing the switching activity. A synthesis approach based on an iterative procedure that compares the minterms consequently, eliminate the complementary variables, then ORing all the terms in one simplified equation is introduced . The results show that about 10% reduction in switching activity has been obtained by using this method if it is compared with the normal optimal solution obtained from K-map method. | ||
| Keywords | ||
| switching activity; low; power consumption; combinational circuits; CMOS circuit; map | ||
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