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Hardware Implementation of 3D-Bresenham's Algorithm Using FPGA | ||
| Tikrit Journal of Engineering Sciences | ||
| Article 1, Volume 20, Issue 2, 2013, Pages 37-47 PDF (0 K) | ||
| Authors | ||
| ; Dr. Basma Mohammed Kamal Younis; am Salim Mohammed Sheet | ||
| Abstract | ||
| Traditional 3D-Bresenham's algorithm is efficient in generating lines on raster systems using only integer calculations. This algorithm is needed as a solution of hidden surface problem using depth-buffer method to calculate z value for each pixel, while calculated values of x and y are used to address frame buffer memory, z value is used to test hidden surface by saving the closest depth in depth buffer. In this paper Bresenham's algorithm for plotting 3D-lines is examined then modified to simplify hardware requirements during implementation phase. Basing on efficiency of the algorithm on the space symmetry an enhanced version of this algorithm is implemented using OpenGL. Experimental results confirm results calculated theoretically for both traditional and modified algorithms. The hardware implementation is accomplished for real time applications, and a graphic sub-system is designed using FPGA. Finally, a comparison is accomplished for Spartan3E utilization which is used to implement the hardware | ||
| Keywords | ||
| Computer graphics; Bresenham; pixel; Scan conversion; FPGA | ||
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