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Parallel Processing-Parallel Memory Approach for Super Fast Design of Future Microprocessor | ||
| Journal of Engineering and Sustainable Development | ||
| Article 1, Volume 17, Issue 1, 2013, Pages 81-99 | ||
| Author | ||
| Yaakob Karomy. Hanna | ||
| Abstract | ||
| The early design of the microprocessor (μP) used a single ALU with a single unit of memory. The development of the microprocessor design generates a multi-ALUs microprocessor that is a parallel processing with multi-units of memory. The parallel processing approach will increase the speed of the processing but this speed up is non-linear with increasing the number of processors that are used in the system (μP). However, the efficiency of the parallel processing is non-linear and depends on some factors such as the parallel processing type, the overall design, the programming approach and the applications, yet in general the parallel processing efficiency will decrease by the increase of the number of processors in the system. The history of the Intel μP’s will be used as an example to trace and analyze the growth of the μP. This tracing will disclose that the main future problem in the μP is the storage not the processing of the data. This problem is generated because the shared memory in the parallel processing will capture the processors in the system. The processor in this parallel processing system is not free to use the memory but it shares a single memory with other processors in this system. This paper propose a novel approach designing a parallel memory that gives the processors in the parallel processing system a higher freedom to use the memory and eventually increases the efficiency of each processor, that end result will increase the total speed of the parallel processing system because it will become a parallel processing parallel memory (PPPM) system. This approach will apply to the Intel processor P4, which will show that it is able to increase the speed of the P4 processor for more than four times. These results are used to propose a future design strategy as a first step to implement a super fast processor and then a super fast PC. The proposed processor is PPPM system with 256 ALUs, this processor is expected to enhance the strategy of the management and control units to become a successful super fast processor with speed up to 60 times over the Intel P4. | ||
| Keywords | ||
| Intel; parallel processing; parallel memory; cache memory; DMA; memory cycle; Prediction; fetching; Net Burst; shared memory; Delay; Latency | ||
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