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Systolic Video Stream Object Detector Using FPGA-E | ||
| Al-Rafidain Engineering Journal (AREJ) | ||
| Article 1, Volume 22, Issue 4, 2014, Pages 33-43 PDF (0 K) | ||
| DOI: 10.33899/rengj.2014.89977 | ||
| Authors | ||
| Dr.Shefa A. Dawwd; Ula T. Salim | ||
| Abstract | ||
| Object detection is important operation used in multiple applications such as computer vision, image and video processing, security, artificial intelligent, and several other areas.However, in these applications, it is not easy to realize real-time frame rates and fast invariant detecting function under changing object states such as position and size using software implementations. So that to solves these problems and speed up the highly intensive calculation required, In this paper simple and efficient template matching algorithm architecture of a video streaming application for object detection is proposed,it is based on using Sum of Absolute Differences (SAD)withPyramid Sum of Absolute Differences (PSAD) as similarity measures and a systolic array design using sliding window operation, where each video frame is divided into slides and feeds through the window by using a suitable first in first out(FIFO) buffers instead of the sliding window across the video frame. The implementation operation is done by using combination of software and hardware co-design that is based by using pipelining technique, data recirculation , and single instruction multiple data (SIMD) operations. The results for both SAD and PSAD algorithms showed the best match can be found at the template (window) size is 19×19 bits/pixel and with accuracy detectionrate of100%. Keywords: FIFO, FPGA, Object detection, Pipeline, PSAD, SAD,Sliding window, Systolic array, Template matching, Video stream. | ||
| Keywords | ||
| KEYWORDS; FPGA; Object detection; Pipeline; PSAD; sad; Sliding window; Systolic array; Template matching; Video stream | ||
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